1. Field of the Invention
This invention relates to adders and more particularly to a circuit and method for adding operands of multiple sizes.
2. Description of the Relevant Art
Microprocessors determine the speed and power of personal computers, in a growing number of more powerful machines, by handling most of the data processing in the machine. Microprocessors typically include at least three functional groups: the input unit (I/O unit), the control unit, and the arithmetic logic unit (ALU). The I/O unit interfaces between external circuitry and the ALU and the control unit. I/O units frequently include signal buffers for increasing the current capacity of a signal before the signal is sent to external components. The control unit controls the operation of the microprocessor by fetching instructions from the I/O unit and translating the instructions into a form that can be understood by the ALU. In addition, the control unit keeps track of which step of the program is being executed. The ALU handles the mathematical computations and logical operations that are performed by the microprocessor. The ALU executes the decoded instructions received from the control unit to modify data contained in registers within the microprocessor.
An essential component of any ALU is the adder circuit. The adder circuit performs addition operations on two or more input operands. Because the addition operation is one of the most commonly invoked operations during the execution of a computer program, the speed with which the adder circuit can compute the sum of two input operands is extremely important in determining the speed of the overall system.
Several common adder circuits are well known in the field of digital logic. A ripple carry adder, for example, adds two (or possibly more) operands in much the same manner as a person would add two numbers. The least significant bit of the first operand is added to the least significant bit of the second operand (and possibly a carry in bit) to produce a least significant result bit and a least significant carry bit. The least significant carry bit is then added to the next most significant bit of the first operand and the next most significant bit of the second operand to produce a next most significant result bit and a next most significant carry bit. This sequence continues until, eventually, the most significant bits of the operand have been added together with the carry bit from the preceding stage to produce the most significant result bit and a carry out bit. The carry out bit of the ripple carry adder can be used as a carry in bit to a subsequent adder such that the multiple ripple through adders can be connected together in series.
Carry lookahead adders are also well known in the art. Carry lookahead adders operate faster than ripple carry adders. As a result, carry lookahead adders are preferred in ALU design. Carry lookahead adders employ a carry lookahead circuit in which each carry bit can be generated as a function of the operand bits and the carry input bit. Namely, the carry lookahead circuit operates in accordance with the following equations: EQU c.sub.i+1 =g.sub.i +p.sub.i c.sub.i (1) EQU g.sub.i =a.sub.i b.sub.i (2) EQU p.sub.i =a.sub.i +b.sub.i (3)
Where c.sub.i+1 represents the carry bit of an i.sup.th stage and a.sub.i and b.sub.i represent the i.sup.th bits of the operands to be added. It is readily seen that if g.sub.i is true in Equation (1) then c.sub.i+1 is certainly true and a carry bit is generated. If p.sub.i is true then if c.sub.i is true then it is propogated to c.sub.i+1. Each sum bit s.sub.i of an adder can be represented as: EQU s.sub.i =a.sub.i b.sub.i c.sub.i +a.sub.i b.sub.i c.sub.i +a.sub.i b.sub.i c.sub.i +a.sub.i b.sub.i c.sub.i. (4)
From equations (1)-(4) each carry bit generated by the carry lookahead circuit can be represented as follows: EQU c.sub.i+1 =g.sub.i +p.sub.i g.sub.i-1 +p.sub.i p.sub.i-1 g.sub.i-2 +. . . +p.sub.i p.sub.i-1. . . p.sub.1 g.sub.0 +p.sub.i p.sub.i-1. . . p.sub.1 p.sub.0 c.sub.in. (5)
FIG. 1 shows a prior art adder circuit 10 configured to add operands of multiple sizes. More particularly, an adder circuit 10 is configured to add first and second four bit or eight bit operands. Adder circuit 10 is configured as a carry lookahead adder employing a carry lookahead circuit 12 operating in accordance with equation (5). Adder circuit 10 further includes a first set of XOR gates 14 and a second set of XOR gates 16. Each of the XOR gates of the first and second set includes a pair of inputs and an output. Each XOR gate 14 is coupled to receive a pair of corresponding bits from first and second input operands (a.sub.8:1 and b.sub.8:1). Each XOR gate 16 is coupled to receive the output of an XOR gate 14 and a carry bit c.sub.i from carry lookahead circuit 12.
Adder circuit 10 finally includes a multiplexer 18 having a pair of inputs, a selector input and carry output coupled to a carry output node 20. One input of multiplexer 18 is coupled to receive the most significant carry bit (c.sub.8) provided by carry lookahead circuit 12. The second input of multiplexer 18 is coupled to receive the fourth least significant carry bit (c.sub.4) of carry lookahead circuit 12. The select input of multiplexer 18 is configured to receive a first or second control signal. Multiplexer 18 receives the first control signal when adder circuit 10 is directed to add first and second four bit operands. Multiplexer 18 receives a second control signal when adder circuit 10 is directed to add first and second eight bit operands. In each mode, carry lookahead circuit generates eight carry bits c.sub.8:1. When adder circuit 10 is directed to add first and second eight bit operand, c.sub.8 represents the carry out bit to be forwarded to subsequent circuitry such as a second adder circuit (not shown). However, when adder circuit 10 is directed to add first and second four bit operand, c.sub.4 represents the carry out bit to be forwarded to subsequent circuitry.
In the second mode of operation, first and second eight bit operands are provided to the first and second inputs of the carry lookahead circuit 12. Carry lookahead circuit 12 generates eight carry bits (c.sub.8:1) as a function of the eight bit input operands and a carry input bit received at carry input node 22. XOR gates 16 generate an eight bit result from the eight carry bits and the outputs of XOR gates 14. In this mode, the second signal is inputted to multiplexer 18 which causes the most significant carry (c.sub.8) bit to be passed to carry output node 20.
In the first mode of operation, first and second four bit operands are provided to the four least significant first and second inputs of the carry lookahead circuit 12. Carry lookahead circuit 12 again generates eight carry bits. It is noted however that only the four least significant carry bits are relevant to the addition of the four bit operands with the fourth least significant carry bit (c.sub.4) representing the carry out of the addition. The four least significant XOR gate 16 generate the four bit result from the four least significant carry bits of carry lookahead circuit 12 and the outputs of the four least significant XOR gates 14. In this mode, the second control signal is provided to multiplexer 18 which causes the fourth least significant carry bit provided by carry lookahead circuit 12 to pass to carry output node 20.
Multiplexer 18 adds signal propagation delay between the carry input node 22 and the carry output node 20. Typically, the propagation delay between carry input node 22 and carry output node 20 is the most critical in the operation of the adder circuit 10. It is desirable to remove as much delay in this critical path node to optimize the speed of adder circuit operation.